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CXA2078Q
I2C Bus-Compatible Audio/Video Switch with Electronic Volume
Description The CXA2078Q is an I2C programmable audio, video switch designed for set top box applications. It interfaces from digital encoder sources to TV, VCR and auxilliary scart connectors. Features * 3 scart independent audio/video switching (TV, VCR, AUX) * 0 to -63dB volume control with click noise reduction * 5 stereo audio inputs * I2C control with two address setting * Scart Function Switching input and output * Scart Fast Blanking for OSD * RF modulator output with Y/C mix option * On-chip +12V to +9V voltage regulator * 4 logic outputs Applications Audio/Video switch featuring I2C bus compatibility for set top box Structure Bipolar silicon monolithic IC Absolute Maximum Ratings * Supply voltage VCC * Operating temperature Topr * Storage temperature Tstg * Allowable power dissipation PD Operating Conditions * Supply voltage * Operating voltage 64 pin QFP (Plastic)
12 -20 to +75 -65 to +150 500
V C C mW
+10.7 to +12 9 0.5
V V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E97843-PS
CXA2078Q
Pin Configuration
HW MUTE
DIG_GND
FBLK_IN1
VOUT3
FNC_TVA
FNC_TVB
VOUT4
DIG_VCC
LOG_1
LOG_2
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
MONO
RTV
LIN4
VOUT8
32 ROUT1 31 VOUT5 30 LOUT1 29 VOUT6 28 ROUT2 27 VOUT7 26 LOUT2 25 AUDIO_VCC 24 VIN12 23 BIAS_AUDIO 22 VIN8 21 LIN3 20 VIN4
LOG_3
LOG_4
VOUT2 52 FBLK_OUT 53 VOUT1 54 VCC_12V 55 VREG_9V 56 VREG_BASE 57 VIDEO_VCC 58 RIN5 59 FBLK_IN2 60 LIN5 61 VIN1 62 RIN1 63 VIN3 64
LTV
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
RIN4 VIN11
FNC_VCR
VIN9
BIAS_VIDEO
VIDEO_GND
VIN10
RIN2
VIN5
VIN7
LIN2
SDA
SCL
TRAP
AUDIO_GND
FNC_AUX
-2-
RIN3
LIN1
VIN6
VIN2
ADR
CXA2078Q
Block Diagram
TYPICAL CONFIGURATION SOURCE AUX ENC DIGITAL (OSD) AUX DIGITAL (OSD) AUX DIGITAL (OSD) DIGITAL (NO OSD) VCR AUX DIGITAL (OSD) VCR AUX RED CVBS CVBS CVBS BLUE BLUE GREEN GREEN RED CHROMA CHROMA CHROMA CHROMA LUMA LUMA LUMA LUMA CVBS OUTPUT MODE1 MODE2 FBLK_IN1 FBLK_IN2 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VIN9 VIN10 VIN11 VIN12 41 60 62 18 64 20 2 6 14 22 4 8 16 24 VIDEO SWITCH2 (VCR) x2 31 VOUT5 (CHROMA) VCR x2 29 VOUT6 (CVBS/LUMA) x2 48 VOUT4 (CVBS/LUMA) Mute BIAS x2 x2 52 VOUT2 (GREEN) TV Comparator Comparator 5V 0V VIDEO SWITCH1 (TV) x2 54 VOUT1 (BLUE) FBLK_SW 53 FBLK_OUT TYPICAL LOAD
50 VOUT3 (RED/CHROMA)
DIGITAL (NO OSD) CVBS
(OSD = On-Screen Display)
VIDEO SWITCH3 (AUX) x2 MIX_SW Input attenuation = 6dB with 6k external resistor. RIN1 RIN2 RIN3 RIN4 RIN5 LIN1 LIN2 LIN3 LIN4 LIN5 6k 6k 6k 6k 6k 6k 6k 6k 6k 6k VCC_12V VREG_BASE VREG_9V VIDEO_VCC BIAS_VIDEO VIDEO_GND AUDIO_VCC BIAS_AUDIO AUDIO_GND 63 15 19 36 59 1 17 21 39 61 55 57 56 58 3 9 AUX 25 23 13 4.5V BIAS 2 BIAS 4.5V I2C INTERFACE 38 FNC_TVA 37 46 45 MONITOR P.O.D 44 43 FNC_TVB LOG_1 LOG_2 LOG_3 LOG_4 TV x2 Mute 26 LOUT2 9V REG VCR x2 30 LOUT1 Att. Att. Att. Att. Att. Att. Att. Att. Att. Att. 8dB step 1dB step 8dB step 1dB step x2 49 LTV AUDIO SWITCH1 (TV) x2 Y/C MIXER VOLUME CONTROL & MUTE x2 51 RTV TV 33 35 27 VOUT7 (CVBS) VOUT8 (CVBS) TRAP AUX
RF MOD
AUDIO Z.C.D SWITCH2 (VCR) Logic x2
34
MONO
RF MOD
32
ROUT1
4.05V BIAS 1
AUDIO SWITCH3 (AUX) x2 28 ROUT2
DIG_VCC DIG_GND SDA SCL ADR FNC_VCR FNC_AUX HW MUTE
47 42 11 10 12 5 7 40
LOGIC
-3-
CXA2078Q
Pin Description Pin No. 62 18 64 20 2 6 14 22 4 8 16 24 63 15 19 36 59 1 17 21 39 61 Symbol VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VIN9 VIN10 VIN11 VIN12 RIN1 RIN2 RIN3 RIN4 RIN5 LIN1 LIN2 LIN3 LIN4 LIN5 Pin voltage
VCC = 12V 14A 62 14
Equivalent circuit
Description
VCC = 9V
4.6V
18 22 64 4 20 8 2 16 6 24
120k
147 60A
Video signal inputs. Input impedance typically 120k.
VCC = 12V 4.5V 63 1 15 17 33k
4.5V
19 21 36 39 59 61 7A 27k
Audio signal inputs. Input impedance typically 60k.
VCC = 12V
VCC = 9V 200 140F
54 52 50 48 31 29 27 33
VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT8
54 31 52 29
3.9V
50 27 48 33
Video signal outputs.
280A
VCC = 9V VCC = 12V 33A 22k 51
51 32 28 49 30 26
RTV ROUT1 ROUT2 LTV LOUT1 LOUT2
4.5V
32 28 49 30 26 55
20k 20k
Audio signal outputs.
33A
-4-
CXA2078Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC = 12V
VCC = 9V 75A
200
34
MONO
4.5V
34 200 20k
Audio mono signal output.
75A
VCC = 9V VCC = 12V 14A 11k
3
BIAS_ VIDEO
3.9V
3 200 9k
Reference Bias for video circuit. Connected to GND with capacitor.
VCC = 9V VCC = 12V 20k
23
BIAS_ AUDIO
4.5V
23 20k 7A
Reference Bias for audio circuit. Connected to GND with capacitor.
VCC = 12V 40k
VCC = 9V
2.7V
37 38
FNC_TVB FNC_TVA
--
37 38 20k
I2C controlled output giving 0/2V. Maximum load current = 800A
-5-
CXA2078Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC = 12V 77.7k
56
VREG_9V
9V
56 13.5k 120A
Pin connected to emitter of external regulator transistor.
VCC = 12V 1mA 57
VCC = 12V
57
VREG_ BASE
9.7V
413 15p 120A
Connection to base of external regulator transistor.
VCC = 9V 40A 4k 10 10k 40k
10
SCL
--
I2C Clock Input. VIL = 1.5V (max) VIH = 3.0V (min)
VCC = 9V 40A 4k 11 4.5k 40k
11
SDA
--
I2C Data input/output. VIL = 1.5V (max) VIH = 3.0V (min) VOL = 0.4V (max)
-6-
CXA2078Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC = 12V 147 72k 28k
12 40
ADR HW MUTE
--
12 40
HW MUTE: This pin is active high > 2.5V. When high, audio outputs RTV, LTV and MONO are muted. ADR: Selects the I2C address for the IC. < 1.5V = Low Add = 90H > 2.5V = High Add = 92H
VCC = 12V
VCC = 9V 8A 40k
43 44 45 46
LOG_4 LOG_3 LOG_2 LOG_1
3V 43
--
44 45 46 4.5k 7.5k
Open collector logic Pins. Maximum current sink = 1mA
VCC = 9V VCC = 12V 1k 35
35
TRAP
3.9V
147
Connection to external trap circuit. Trap components should be kept as close as possible to this pin.
470A
VCC = 12V 100 100A
VCC = 9V
53
FBLK_ OUT
--
53
100A
Fast Blank output set by I2C, FBLK_IN1 or FBLK_IN2. High = 5.1V Low = 1.2V Connected to external emitter follower. Maximum load current = 800A
-7-
CXA2078Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC = 12V 50A
VCC = 9V
41 60
FBLK_IN1 FBLK_IN2
--
147 41 60 90A
Fast Blank inputs. Low = < 0.4V High = > 1.0, < 3.0
VCC = 9V 80A 50k 50k 5
5 7
FNC_VCR FNC_AUX
--
7 10k 100k
Function switching input (Scart pin 8). Typical levels = 0V/6V/12V
-8-
CXA2078Q
Electrical Characteristics Absolute Maximum Ratings Supply Voltage Vcc_12V Operating Conditions * Supply Voltage * Voltage Regulation * Operating Voltage
12
V
Vcc_12V Vreg_9V Video_Vcc, Dig_Vcc, Audio_Vcc
12 to 10.7 9 0.45 9 0.5 9 0.5
V V (from 12V supply) V V
FNC_TVA (pin 38) and FNC_TVB (pin 39) are static sensitive. Precaution should be taken (note 8 in "Notes on Operation"). Operation of the CXA2078Q using a 9V supply connected directly to the VCC_12V, Video_VCC, AUDIO_VCC and Dig_VCC pins is possible but not recommended. (The unused on-chip voltage regulator is then forced to have pins Vreg_base and Vreg_9V floating.)
-9-
CXA2078Q
Electrical Characteristics Nominal conditions (Ta = 25C) Item Current Consumption Video system Item Input pin voltage Output pin voltage Vout1 - 8 Vout8 (mix) Symbol VVPin VVPout VVPoutm GVv GVYC fV3dB Symbol ICC Conditions VCC_12V = 12V, No signal, no load Min. 30 Typ. 50 Max. 70 Unit mA
Nominal conditions (Ta = 25C, Vcc_12V = 12V) Conditions No signal, no load (Fig.1) No signal,no load,Y/C mix inactive (Fig.1) No signal, no load, Y/C mix active (Fig.1) f = 200kHz, 0.3Vp-p input (Fig.2) f = 200kHz, 0.3Vp-p input (Fig.2) 0.3Vp-p input, frequency where output level is -3dB with 200kHz serving as 0dB (Fig. 2) 0.3Vp-p input, frequency where output level is -3dB with 200kHz serving as 0dB. No trap connected. (See note below) (Fig.2) 200kHz input (Fig.2) 200kHz, 2.5Vp-p input (Fig.2) f = 4.43MHz, 1Vp-p input (Fig.2) Ratio of 0.7Vp-p white video signal to black line noise. Weighted using CCIR 567. HPF @ 5kHz, LPF @ 5MHz. (Fig.2) 1Vrms 1kHz input through 56k. Attenuation measured to calculate ZinV (Fig.3)
Input/V V2
Min. 4.3 3.6 3.5 5.5 5.4 15
Typ. 4.6 3.9 3.8 6.0 6.0 20
Max. 4.9 4.2 4.2 6.5 6.4
Unit V V V dB dB MHz
Gain (except Y/C mixer) Gain of Y/C mixer Bandwidth (except Y/C mixer)
Bandwidth of Y/C Mixer Input dynamic range Output dynamic range Cross talk S/N ratio
fYC3dB VDRVI VDRVO Vctv S/NV
7 2.5 5.0 -- --
15 -- -- -- 72
-- -- -- -50 --
MHz Vp-p Vp-p dB dB
Input Impedance
ZinV
94
120
k
V1
Non-linearity
Lin V1 = Pin Voltage +0.5V V2 = Pin Voltage +1V At output, non-linearity =
(Fig.4)
-3
-0.4
+3
%
Differential Gain Differential Phase Sync crush Delay of Luma over Chroma through mixer
DG DP SC
tcld
V2 -1 x 100 V1 x 2 1.7Vp-p 5-step modulated staircase. (Chroma and Burst are 150mVp-p 4.43MHz) (Fig.2) as above. (Fig.2) Percentage reduction in sync pulse (0.4Vp-p), with tip at -1.2V input offset. (Fig.4) 0.4Vp-p square wave input. Input to output edge delay measured. No trap. (Fig.2)
1.5 1 0.2 3
% Deg %
15
40
ns
Note) Input output path from Vin9 - 12 to Vout 8 through mixer has BW reduced by external stray capacitance on TRAP pin. - 10 -
CXA2078Q
Electrical Characteristics Audio system Unless otherwise stated: input coupling capacitor 1F in series with 6k resistor; output coupling capacitor of 10F; load of 10k. Nominal conditions (Ta = 25C, Vcc_12V = 12V) Item Input pin voltage Gain Symbol VAPIN Conditions No signal, no load (Fig. 5) f = 1kHz, 1Vrms input. (Fig. 6) f = 1kHz, 1Vrms input. (Fig. 6) f = 1kHz, 1Vrms "stereo" input. (Fig. 6) 0.3Vp-p input. Output level at 30kHz with 1kHz serving as 0dB. 6k removed. (Fig. 7) 0.3Vp-p input; frequency where output level is -3dB with 1kHz serving as 0dB. 6k removed. No load (Fig. 7) f = 1kHz, 0.5Vrms, unweighted response; LPF @400Hz, HPF @ 80KHz. (Fig. 6) f = 1kHz (Fig. 6) f = 1kHz, 1Vrms input on one input, measure on any other audio output. (Fig.6) f = 100Hz, 0.3Vp-p applied to Vcc_aud (Fig. 8) f = 100Hz, 0.3Vp-p applied to Vcc_aud (Fig. 8) f = 100Hz, 0.3Vp-p applied to Vcc_aud (Fig. 8) Offset voltage between any audio input and R/Lout1, 2 (Fig. 5) (excluding series external 6k) (excluding any external series resistor) f = 1kHz, 1Vrms input to two channels. Phase difference of stereo output measured f = 1kHz, 1Vrms input (at maximum volume). HPF @ 20Hz, LPF @ 20kHz. (Fig. 6) f = 1kHz, 0.5Vrms input. Set by I2C (Fig.6) f = 1kHz, 0.5Vrms input. Set by I2C (Fig.6) f = 1kHz, 1Vrms input. (Fig.6) Offset voltage between any audio input and RTV, LTV outputs (Fig.5) Min. 4.2 -0.5 -0.65 -0.65 -0.3 Typ. 4.5 0 0 0 0 Max. 4.8 +0.5 +0.35 +0.45 +0.3 Unit V dB dB dB dB
R/LOUT1, 2 GVA RTV, LTV GVATV MONO GVAM FAF
Audio frequency response Frequency B/W
FBWA1
--
1
--
MHz
Distortion Input Dynamic Range Cross talk (Channel separation)
THD VdA VctA
-- 2 -- -- -- -- -30 48 -- --
0.004 -- -88 -62 -75 -44 +2 60 10 0.05
0.2 -- -76 -- -- -- +30 72 -- --
% Vrms dB dB dB dB mV k Deg
R/LOUT1, 2 RRA Ripple rejection RTV, LTV MONO DC Offset -R/Lout1, 2 Input impedance Output Impedance Phase Difference S/N ratio RRATV RRAM Voff Zin Zout Vpda
S/NA
72
95
--
dB
Electronic Volume Control Fine volume attenuation AEVC step Coarse volume AEVF attenuation step Amute Mute DC Offset -RTV, LTV VoffTV
0.6 7.5
1 8 >80
1.4 8.5
dB dB dB
-30
+2
+30
mV
- 11 -
CXA2078Q
+12V
+12V
47H 25pF 1k Trap Switch SW1
+12V
BC547B
BC547B
BC547B
Measurement Point
1k
+9V
1k
1k
BC547B +12V BC547B +12V +12V BC547B +9V +9V 1k 1k 52 53 54 55 56 57 58 59 60 61 62 63 64
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32 31 30 29 28 27 26 25 24 23 22 21 20 22F 1k +9V 1k 1k +12V BC547B +12V BC547B +12V BC547B
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
SCL SDA 47F
Measurement Point
Fig. 1. Video system (d.c.test)
Notes) 1. All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor. 2. All video outputs are loaded with emitter follower during tests. 3. Voltage measurements carried out with a high input impedance DVM. Typically 10G.
- 12 -
CXA2078Q
+12V
+12V
47H 25pF 1k Trap Switch SW1
+12V
BC547B
BC547B
BC547B
Measurement Point
1k
+9V
1k
1k
BC547B +12V BC547B +12V +12V BC547B +9V +9V 1k 1k 52 53 54 55 56 57 58 59 60 75 2.2F 61 62 2.2F 63 64
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32 31 30 29 28 27 26 25 24 23 22 21 20 2.2F 1 2.2F 75 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 75 2.2F 75 2.2F 75 22F 1k +9V BC547B +12V 1k 1k +12V BC547B +12V BC547B
75
2.2F 2.2F
2.2F
75 75
75
47F
Input Signal
Fig. 2. Video system (gain, dynamic range, bandwidth, differential gain, differential phase, crosstalk, signal to noise, Luma-Chroma delay) Signal applied to Pins 2, 4, 6, 8, 14, 16, 18, 20, 22, 24, 62, 64 Output Signal Measured from pins 27, 29, 31, 33, 48, 50, 52, 54 Notes) 1. All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor. 2. For tests requiring video measuring equipment with 75 input impedance, an external video line driver or buffer is used. 3. For bandwidth tests through Y/C mixer, the trap circuit is switched out using SW1. 4. All video outputs are loaded with emitter follower during tests. 5. For Luma and Chroma input to output delay, measure signal at the I.C. pins. - 13 -
75
75 75
SCL SDA
2.2F
2.2F
2.2F
CXA2078Q
+9V
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
52 53 54 +12V BC547B +9V +9V 55 56 57 58 59 60 56k 2.2F 61 62 2.2F 63 64
32 31 30 29 28 27 26 25 24 23 22 21 20 +9V 22F
56k
47F
Signal Input
Measurement Point
Fig. 3. Video system (input impedance) Signal applied and measured from pins, 2, 4, 6, 8, 14, 16, 18, 20, 22, 24, 62, 64
Notes) 1. All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor. 2. Voltage measurements carried out with a high input impedance DVM. Typically 10G.
56k
SCL SDA
- 14 -
56k 2.2F
56k 2.2F
56k 2.2F 2.2F
56k 2.2F
56k 2.2F
56k 2.2F
56k
2.2F
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
56k 2.2F
56k 2.2F
CXA2078Q
+12V
+12V
47H 25pF 1k Trap Switch SW1
+12V
BC547B
BC547B
BC547B
Measurement Point
1k
+9V
1k
1k
BC547B +12V BC547B +12V +12V BC547B +9V +9V 1k 1k 52 53 54 55 56 57 58 59 60 61 62 63 64
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32 31 30 29 28 27 26 25 24 23 22 21 20 1k +9V 22F 1k 1k +12V BC547B +12V BC547B +12V BC547B
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
SCL SDA 47F
PSU
Input Signal
Fig. 4. Video system (linearity, sync crush) Signal applied to Pins, 2, 4, 6, 8, 14, 16, 18, 20, 22, 24, 62, 64 Output Signal Measured from pins 27, 29, 31, 33, 48, 50, 52, 54
Notes) 1. All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor. 2. All video outputs are loaded with emitter follower during tests.
- 15 -
CXA2078Q
Output Measurement Point
+9V HW mute +9V SW1
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
52 53 +12V BC547B +9V +9V 54 55 56 57 58 59 60 61 62 63 64
32 31 30 29 28 27 26 25 24 23 22 21 20 22F +9V
1
2
3
4 47F
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
SCL SDA
Input Measurement Point
Fig. 5. Audio system (d.c. tests)
Notes) 1. All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor. 2. Voltage measurements carried out with a high input impedance DVM. Typically 10G.
- 16 -
CXA2078Q
6k 1F 600
6k 1F 600
+9V
10F 10k
+9V
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 10F 10k 52 53 +12V 54 55 BC547B +9V +9V 600 1F 6k 600 1F 6k 600 1F 6k 56 57 58 59 60 61 62 63 64 32 31 10F 10k 30 29 10F 10k 28 27 10F 10k 26 25 24 23 22 21 20 6k 1F 600 22F +9V
1 6k 1F 600
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 6k SCL SDA 1F 600 6k 1F 600 6k 1F 600
47F
Input Signal
Fig. 6. Audio system (gain, dynamic range, Signal to noise, Crosstalk, Distortion, Volume control) Signal applied to Pins, 63, 1, 59, 61, 15, 17, 19, 21, 36, 39 Output Signal Measured from pins 26, 28, 30, 32, 34, 49, 51
Notes) 1. All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor. 2. When muting audio using Hardware mute, SW1 is closed.
- 17 -
10F 10k
10F 10k
HW SW1 mute
Measurement Point
CXA2078Q
1F 600
1F 600
+9V
+9V
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 10F 10k 52 53 +12V 54 55 BC547B +9V +9V 1F 600 600 1F 600 1F 56 57 58 59 60 61 62 63 64 32 31 10F 10k 30 29 10F 10k 28 27 10F 10k 26 25 24 23 22 21 20 1F 600 22F +9V
1
2
3
4 47F
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
1F 600
SCL SDA
1F 600
1F 600
1F 600
Input Signal
Fig. 7. Audio system (Bandwidth) Signal applied to Pins, 63, 1, 59, 61, 15, 17, 19, 21, 36, 39 Output Signal Measured from pins 26, 28, 30, 32, 34, 49, 51
Note) All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor.
- 18 -
10F 10k
10F 10k
10F 10k
HW SW1 mute
Measurement Point
CXA2078Q
6k 1F 600
600
+9V
+9V
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 10F 10k 52 53 +12V 54 55 BC547B +9V 56 32 31 10F 10k 30 29 10F 10k 28 27 10F 10k 26 +9V 24 100Hz 0.3Vp-p 23 22 21 20 6k 1F 600 22F 25
57 +9V 58 6001F 6k 59 600 1F 6k 600 1F 6k 60 61 62 63 64
1 6k 1F 600
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 6k SCL SDA 1F 600 6k 1F 600 6k 1F 600
47F
Fig. 8. Audio system (Ripple Rejection) Output Signal Measured from pins 26, 28, 30, 32, 34, 49, 51
Note) All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor.
- 19 -
10F 10k
10F 10k
10F 10k
6k 1F
HW SW1 mute
Measurement Point
Typical Application Circuit
1k +12V 9V_REG 16 14 12 27pF VCR SCART 10 8 6 4 2 10 600 BC547B 31 VOUT5 75 LOUT1 30 10 600 BC547B 75 29 VOUT6 1k 28 ROUT2 10 600 +12V 27 VOUT7 BC547B CXA2078Q 26 LOUT2 10 600 4.7 25 AUDIO_VCC 0.47 24 VIN12 9V_REG 10nF 1k 1k +12V 47H 9 7 5 3 1 11 13 15 10k 1k 10k 1 6k 2.2k 2.2k 6k 1 10k 10k 75 4.7 10k 10nF 10k AUDIO4_L HW_MUTE AUDIO4_R 17 TO MODULATOR 18 19 50 1k BC547B 20 21 75
T. V. SCART
20
21
+12V
18
19
BC547B 75
16 600 10 600 10
17
BC547B
14
15
75
12
13
BC547B
FBLK_IN1
DIG_VCC
DIG_GND
VOUT4
LOG_4
LTV
FNC_TVA
FNC_TVB
RIN4
LOG_3
VOUT3
LIN4
LOG_2
RTV
HW MUTE
8 51 47 34 ROUT1 42 41 39 33 50 44 36 38 49 48 45 43 46 40 37 35
BC547B
6 32
7
75
4
5
2
3
75
VOUT2
52
1
5x1k
BC547B
FBLK_OUT
53
VOUT1
54
+12V
VCC_12V
55
47
VREG_9V
56
BC547B
VREG_BASE
57
10nF
AUDIO 5
SCL
SDA
LIN1
ADR
VIN9
VIN5
VIN7
RIN2
LIN2
VIN6
VIN2
RIN3
VIN10
VIN11
FNC_VCR
FNC_AUX
BIAS_VIDEO
VIDEO_GND
AUDIO_GND
- 20 -
1 2 3 7 4 8 5 6 9 10 11 12 13 14 15 6k 1 0.47 47 0.47 0.47 6k 0.47 1 0.47 ENCODER I2C 10k 10k
VIDEO_VCC
58
4.7
6k
RIN5
59
1
FBLK_IN2
60
LOG_1
TRAP
MONO
VOUT8
10
11
75
9
R L
6k
75 23 BIAS_AUDIO 22 22 VIN8 0.47 75 21 LIN3 6k 1 AUX SCART 20 20 VIN4 0.47 75 16 17 18 19 18 16 14 12 10 6k 1 0.47 0.47 75 6k 1 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1
75
LIN5
61
1
VIN1
62
RIN1
63
VIN3
64
6k
1
0.47
0.47
CXA2078Q
CXA2078Q
Description of operation 1. Explanation of Video Section The video section comprises of 12 high impedance (120k) inputs switched through to 8 video outputs. A +6dB internal amplifier is connected to each output. The amplifier is required to compensate for the 6dB attenuation which occurs at the external emitter follower stage used for driving video loads. The typical external configuration is shown in Fig. 1-1. A Y/C mixer can be used for mixing Luma and Chroma signals for use with an external RF modulator connected to Vout8. The Y/C mixer is controllable via the I2C data bus. The circuit is shown in Fig. 1-2 with a trap circuit used to give 3dB attenuation at 4.43MHz of the Luma signal.
Video_VCC = 9V SCART_in 75 0.47 75 Vbias Switch Vin AMP 120k Vout
VCC = 12V beta = 250 SCART_out Load 75 1k 75
BC547B
Vbias Video element
Fig. 1-1. Video circuit element: 6dB gain amplifier with external emitter follower
R/C
Vout3 6dB
CVBS/Y
Vout4 6dB 1k 1k 6.5k 0dB Vout8 6dB 147 0dB TRAP 1k 47F 25pF 6.5k
Fig. 1-2. Y/C MIXER Circuit - 21 -
CXA2078Q
2. Explanation of Audio System. Audio Switch and Amplifier The audio system consists of 5 stereo inputs, 3 stereo outputs and a mono output. Each output can be independently connected to any one of five inputs, Lin1 to Lin5 for the left stereo audio channel, and Rin1 to Rin5 for the right hand audio channel. In all cases, the input to the switch and amplifier is composed of a potential divider consisting of a 27k series resistor and a 33k connected to a voltage source (4.5V). When used in conjunction with an external 6k series input resistor, the input configuration forms a -6dB attenuator (Fig. 2-1). The net gain of the audio system is zero as there is an internal +6dB amplifier on each output. The output impedance of the audio amplifier is near zero, and is used to drive the external SCART circuit. The output is capacitively coupled through a 10F capacitor, and an optional 600 series compliance resistor. Depending on the length and type of cable used in the scart cable connector, the load seen at the scart terminal will consist of a parallel capacitor, (100pF to 400pF) and mandatory 10k resistor connected to ground (Fig. 2-2). The customer may chose to place an alternative audio output filter at the AV switch output. TV audio output The TV audio section is composed of an audio switch and 0dB amplifier followed by two variable gain stages, corresponding to the course and fine electronic volume control amplifiers, EVC and EVF. The EVC amplifier attenuates the input signal in steps of 8dB. A range of attenuation from 0dB to 56dB can be programmed by means of the I2C interface. Similarly, the fine volume control (EVF) can be programmed to provide a range of attenuations between 0dB and 7dB. The attenuated signal is passed through to the output buffer stage which provides the necessary +6dB gain, and is used to drive the SCART connector. The final output buffer can also act as a -80dB (mute) amplifier (Fig. 2-4). Zero Cross Detector (ZCD) The zero cross detector reduces the effect of "click noise" when implementing a volume change or an audio mute. The change volume or mute instruction sent by I2C will only be implemented when a minimal (ie zero cross) signal amplitude is detected. The zero cross detection circuit can be turned off by setting the "ZCD" bit low in the I2C write mode. The status of the zero cross detector can be checked in the I2C read mode (Z.C status). When this bit is high, a zero cross condition has been detected subsequent to the issue of an I2C volume change or mute instruction. This may be useful if the input waveform is very low frequency, whereupon the microprocessor can re-issue the same instruction, with the zero cross detector circuit switched off. I2C Mute The mute instruction in the I2C format refers to the TV audio circuit. Audio mute can be implemented after a audio zero cross detection, or immediately depending on whether ZCD = 1 or 0. It can be seen from the I2C write format that the same mute bit occurs in DATA1 and DATA5. This allows the software to action an immediate mute, make any suitable changes to the audio source or electronic volume control and after a minimum period of 4 x 90s (360s) un-mute the output buffer. Such a period provides ample time to allow any transient ac voltages to settle during an audio source change.
- 22 -
CXA2078Q
1F Audio in R/L in 6k (external) 600
ATT = -6dB 27k 33k (internal) 4.5V
10F Audio out 600 (external)
SCART
400pF
Terminal 10k
Fig. 2-1. Audio input configuration
Fig. 2-2. Audio output configuration
-6dB R/L in R/L in R/L in R/L in R/L in ATT ATT ATT ATT ATT Mute 4.5V
+6dB
Audio output
Fig. 2-3. VCR and AUX audio configuration
I2C Registers ATT ATT ATT ATT ATT 0dB 0 to -56dB 0 to -7dB
EVC Audio Switch
EVF
+6dB TV Audio Output
Mute Zero Cross Detect to control logic
Mute (-80dB)
Fig. 2-4. T.V. audio section and Electronic Volume Control
- 23 -
CXA2078Q
I2C Interface Data Format IC Control Data Format S Slave address A S: Start condition DATA1 A DATA2 A DATA3 A DATA4 A DATA5 A P
A: Acknowledge
P: Stop condition
There are two possible addresses depending on external address pin (12) tied high or low. Pin 12 = high, Address = 92 Hex Ao = 1 Pin 12 = low, Address = 90 Hex Ao = 0 General I2C data structure (write mode) b7 Address Data1 Data2 Data3 Data4 Data5 Key EVC: EVF: TVMute: Z.C.D: Vid_Sw1: Vid_Sw2: Vid_Sw3: Aud_Sw1: Aud_Sw2: Aud_Sw3: FNC: FBLK: Y/C Mix: LOG1-LOG4: FBLK FNC Y/C Mix TVMute x x x 1 b6 0 EVC Vid_Sw1 (TV) Vid_Sw2 (VCR) Vid_Sw3 (AUX) x LOG4 LOG3 b5 0 b4 1 b3 0 EVF b2 0 b1 Ao TVMute Aud_Sw1 (TV) Aud_Sw2 (VCR) Aud_Sw3 (AUX) LOG2 LOG1 b0 (W) 0 Z.C.D
Electronic Volume Course (8dB steps) Electronic Volume Fine (1dB steps) TV Audio mute. Controls the TV audio output buffer. (Same bit appears in data 1 & 5) Zero cross detector active. When ZCD = 1 volume and mute change at zero cross. Selects the input video sources for Vout1, Vout2, Vout3, Vout4 Selects the input video sources for Vout5, Vout6 Selects the input video sources for Vout7 Selects one of 5 stereo inputs for RTV, LTV Selects one of 5 stereo inputs for Rout1, Lout1 Selects one of 5 stereo inputs for Rout2, Lout2 Video function switch control Video Fast Blanking control When Y/C Mix = 1 converts Y/C input to CVBS for output through Vout8 Logic outputs (open collector). 0 = high impedance. 1 = current sink mode.
- 24 -
CXA2078Q
General I2C data structure (read mode) S Slave address A NA: No Acknowledge DATA STRUCTURE b7 Slave Address Data6 FUNC_VCR: FUNC_AUX: ZC Status: P.O.D.: 1 x b6 0 x b5 0
ZC STATUS
DATA6
NA
P
b4 1 P.O.D.
b3 0
b2 0
b1 X
b0 (R) 1
FUNC_AUX
FUNC_VCR
At pin 5 AV switch monitors the voltage of pin 8 from VCR scart, and records status. At pin 7 AV switch monitors the voltage of pin 8 from AUX scart, and records status. ZC Status = 1 indicates that zero cross condition has been achieved after a volume or mute instruction issued. Power On Detect. P.O.D. = 1 when DIG_VCC voltage rises above a threshold level of approximately 5V.
- 25 -
CXA2078Q
3. Video Input I2C Control 3-1. Video Switch 1 (Vid_Sw1) - TV Output Vout1 B d2_b5 d2_b4 d2_b3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Vin1 Vbias Vbias Vin2 Vbias Vin1 Vin1 Vbias Vin3 Vbias Vbias Vin4 Vbias Vin3 Vin3 Vbias Vin5 Vin6 Vin7 Vin8 Vin5 Vin5 Vin5 Vbias Vin9 Vin10 Vin11 Vin12 Vin3 Vin10 Vin11 Vbias Digital encoder Digital encoder VCR Aux Digital encoder Digital encoder Digital encoder Video Mute Vout2 G/CVBS/Y Vout3 R/C Vout4 CVBS/Y Comment
Table 3-1. showing which video input pins connect to the four TV output pins 3-2. Video Switch 2 (Vid_Sw2) - VCR Output Vout5 Chroma (C) d3_b5 d3_b4 d3_b3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Vin5 Vin6 Vin7 Vin8 Vin5 Vbias Vbias Vbias Vin9 Vin10 Vin11 Vin12 Vin3 Vbias Vbias Vbias Digital encoder Digital encoder VCR Aux Digital encoder Video Mute Video Mute Video Mute Vout6 CVBS/Y Comment
Table 3-2. showing which video input pins connect to the two VCR output pins
- 26 -
CXA2078Q
3-3. Video Switch 3 (Vid_Sw3) - AUX Output Vout7 CVBS d4_b5 d4_b4 d4_b3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Vin9 Vbias Vin11 Vin12 Vin3 Vbias Vbias Vbias Digital encoder Video Mute VCR Aux Digital encoder Video Mute Video Mute Video Mute Comment
Table 3-3. showing which video input pins connect to the single AUX output pin
- 27 -
CXA2078Q
4. Fast Blanking operation (Pin 16 on SCART), FBLK The fast blanking signal instructs the TV to select either the external CVBS information or the external RGB information. This is used to impose an on screen display (OSD) presentation (normally RGB) upon a CVBS background. Fast blanking information has the same nominal phase as the RGB and CVBS signal, and is defined as follows, Fast blanking output at scart, 1. CVBS mode 2. RGB mode Scart pin voltage = 0 to 0.4V Scart pin voltage = 1 to 3.0V
Threshold voltage is approximately 0.75V DC voltage at scart input. The blanking information is usually generated by the same source as that producing the RGB signal. I2C Control In the CXA2078Q, there are two fast blanking inputs, one associated with the auxiliary RGB/CVBS inputs and another associated with Digital Encoder input. These can be selected by I2C. In addition to the two blanking inputs, the fast blank pin output can be set to a constant 0V or 5V by means of the I2C control. Hence there are four possible states. These are controlled according to the following table. FBLK d2_b7 0 0 1 1 d2_b6 0 1 0 1 FBLK_OUT (pin 53) 0V1 5V same state as FBLK_IN1 (0/5V) same state as FBLK_IN2 (0/5V)
1 Default = 0V at power up
- 28 -
CXA2078Q
5. Function switch, FNC. The function switch facility is designed to read the status of the SCART function pin 8 from the VCR and AUX inputs (IC pin 5, 7). The output function pins FNC_TVA and FNC_TVB are controlled from the IC using a write instruction. A suitable interface circuit (fig 5-2) will allow FNC_TVA and FNC_TVB to instruct the TV to switch between display modes. Read Mode DATA STRUCTURE b7 Slave Address Data6 1 b6 0 b5 0 Z.C STATUS b4 1 P.O.D. b3 0 b2 0 b1 X b0 (R) 1
FUNC_AUX
FUNC_VCR
Read mode Status of I2C registers as a function of the voltage on FNC_AUX (pin 7) and FNC_VCR (pin 5) Input Pin Voltage FNC_AUX or FNC_VCR 0V to +2V (default) +4.5 to +7V +9.5 to +12V Level (SCART Defn) (Internal TV) (16:9 External) (4:3 External) read data6 b3/b1 0 0 1 b2/b0 0 1 1
Write mode d3_b7 0 0 1 1
TV Function switch, Interface table FNC_TVA Pin voltage 2V 0V 0V 0V FNC_TVB Pin voltage 2V 2V 0V 0V Comment Internal TV (default) External 16:9 External 4:3 External 4:3
d3_b6 0 1 0 1
Default is Internal TV (0, 0) at power up
- 29 -
CXA2078Q
The two function output pins are controlled via logic to swing from 0 to +2V.
2V FNC_TVA (38) Logic Drive Circuit FNC_TVB (37) < 0.4V 2V < 0.4V
Mux
d3_b7
d3_b6
Fig. 5-1. TV Function switch output Some external circuitry is required to interface from the IC pins to the SCART pin 8. A typical interface circuit is shown in Fig. 5-2.
12V 1k TV scart pin 8 1k 2.2k CXA2078Q 2.2k 50
FNC_TVA FNC_TVB
Fig. 5-2. External circuit for function switch
- 30 -
CXA2078Q
6. Logic outputs I2C control of logic outputs achieved using bits LOG1 - 4. Specification I2C bit 0 = open collector/high output impedance on logic pin I2C bit 1 = current sink mode resulting in 0.2V saturation voltage on logic pin Vmax at logic pin = 12V Imax during current sink = 1mA
VCC = 9V External resistors
10k LOG_1
10k
10k
10k
LOG_2 LOG_3 LOG_4
d5_b3 d5_b2 d5_b1 d5_b0 Logic Logic cct. cct.
Fig. 6-1. Open collector logic outputs
- 31 -
CXA2078Q
7. I2C Audio Signal Control I2C Audio input select using Aud_Sw1 (TV), Aud_Sw2 (VCR), Aud_Sw3 (AUX) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 RTV, ROUT1, ROUT2 Rin1 Rin2 Rin3 Rin4 Rin5 Audio mute Audio mute Audio mute LTV, LOUT1, LOUT2 Lin1 Lin2 Lin3 Lin4 Lin5 Audio mute Audio mute Audio mute
I2C Electronic Volume control (coarse) DATA 1, EVC b7 0 0 0 0 1 1 1 1 b6 0 0 1 1 0 0 1 1 b5 0 1 0 1 0 1 0 1 Gain (dB) 0 -8 -16 -24 -32 -40 -48 -56
I2C Electronic Volume control (fine) DATA 1, EVF b4 0 0 0 0 1 1 1 1 b3 0 0 1 1 0 0 1 1 b2 0 1 0 1 0 1 0 1 Gain (dB) 0 -1 -2 -3 -4 -5 -6 -7
- 32 -
CXA2078Q
I2C Mute function TV Mute DATA1 b1 DATA5 b7 0 0 1 1 Z.C.D DATA1 b0 0 1 0 1 RTV, LTV, MONO output Un-mute immediately Un-mute on next zero cross Mute immediately Mute on the next zero cross
Notes on operation 1) Supply de-coupling capacitors, 10nF and 4.7F in parallel should be inserted as close to the supply pins, 25, 47, 58 as possible. 2) To minimise crosstalk, attention should be given to the routing of audio and video to the IC inputs. PCB track lengths should be kept as short as possible and preferably, audio placed on a separate layer to the video. 3) The trap components on pin 35 should be kept as close to the IC as possible to minimise parasitic capacitance to ground. 4) Attention should be given to the electrolytic capacitors on the input and output signal pins. As the pin's voltage is between 3.7V and 4.7V dc the positive terminal on the capacitor should be orientated towards the pin. 5) The audio outputs may be muted at any time after power up by connecting the HW MUTE pin (40) to a voltage > 2.5V and < 9V. 6) The I2C address of the IC can be changed using the ADR pin (12). By connecting this pin to >5V and <9V the Address changes from 90H to 92H. 7) When driving video loads with impedance = 75 an emitter follower or video line driver is required to be connected at the video outputs. Stray capacitance on pins Vout1-8 must be kept to a minimum by placing loads as close to the pins as possible. 8) As shown on the application schematic, static protection for pins 38 and 37 may typically be achieved using Zener diodes. Diodes with a Zener voltage > 5V are suitable.
- 33 -
CXA2078Q
Typical audio output distortion
Input = 1kHz, 400Hz - 80kHz BPF
1
THD [%]
0.1
0.01
0.001 0 1 2 Input [Vrms] 3 3.66
Audio frequency characteristics
4
Audio input/output gain [dB]
2
0
-2 Input = 0.3Vp-p -4
-6 100
1k
10k Frequency [Hz]
100k
1M
NOTE: Audio input 6k resistor removed for this test.
Video frequency characteristics
8 VOUT1-8 (MIX = OFF)
Video input/output gain [dB]
6
4 VOUT8 (MIX = ON) 2
0 Input = 0.3Vp-p
100k
1M Frequency [Hz]
10M
50M
- 34 -
CXA2078Q
Package Outline
Unit: mm
64PIN QFP(PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1
51 33
+ 0.1 0.15 - 0.05 0.15
52
32
17.9 0.4
+ 0.4 14.0 - 0.1
64
20
+ 0.2 0.1 - 0.05
1 1.0 + 0.15 0.4 - 0.1
+ 0.35 2.75 - 0.15 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g
- 35 -
0.8 0.2
19
16.3

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